The Viterbi decoding algorithm is an optimal and widely used forward- error- correction technique for removing noise from digital radio signals. However, its implementation in hardware is complex and expensive so that the use of a multipurpose microprocessor is generally preferred over a dedicated device. This is for instance the case for the decoder device disclosed in the article "Realtime implementation of the Viterbi decoding algorithm on a high-performance microprocessor" by S.M. Said et al, published in the review "Microprocessors and microsystems", vol 10, no 1, January/February 1986, pages 11 to 16. Therein, the Viterbi algorithm is implemented in the circuitry (firmware) of a standard microprocessor MC68000 manufactured by MOTOROLA.RTM..
A drawback of such a known decoder device is that it is not optimized for performing the Viterbi decoding algorithm. This is particularly true when a high throughput, a small board surface and a low power consumption are required. Indeed, the hardware thereof is designed for handling standard wordlengths, e.g. of 16 bits, and these generally exceed the needs for the specific Viterbi algorithm and thereby increase some delays. Additionally, the microprocessor and its associated memories and peripherals comprise more circuitry than needed for this application, so that both the required board surface and the power consumption are unnecessarily high.